In the field of integrated circuit construction, in general, and in the construction of large ASIC's (i.e., Application Specific Integrated Circuit), in particular, the wiring distance between cores has become greater and greater as the space or paths to physically run the numerous wiring becomes more and more impinged upon due to overcrowding by additional cores. A resultant disadvantage is that latency problems occur wherein a signal fails to be latched onto the receiving core within the current clock cycle.
Accordingly, there is a need in the field of ASIC's for an improved way for communicating that overcomes the aforementioned, and other, disadvantages.